Refreshing Data of Memory Cells with Electrically Floating Body Transistors

ABSTRACT

A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device can be refreshed within a single clock cycle.

RELATED APPLICATIONS

This application claims the benefit of United States (U.S.) Patent Application No. 60/973,139, filed Sep. 17, 2007.

TECHNICAL FIELD

The embodiments relate to a semiconductor device, architecture, memory cell, array, and techniques for controlling and/or operating such device, cell, and array. More particularly, in one aspect, the embodiments relate to a dynamic random access memory (“DRAM”) cell, array, architecture and device, wherein the memory cell includes an electrically floating body configured or operated to store an electrical charge.

BACKGROUND

There is a continuing trend to employ and/or fabricate advanced integrated circuits using techniques, materials and devices that improve performance, reduce leakage current and enhance overall scaling. Semiconductor-on-Insulator (SOI) is a material in which such devices may be fabricated or disposed on or in (hereinafter collectively “on”). Such devices are known as SOI devices and include, for example, partially depleted (PD) devices, fully depleted (FD) devices, multiple gate devices (for example, double or triple gate), and Fin-FET.

One type of dynamic random access memory cell is based on, among other things, the electrically floating body effect of SOI transistors; see, for example, U.S. Pat. No. 6,969,662 (the “'662 patent). In this regard, the dynamic random access memory cell may consist of a PD or a FD SOI transistor (or transistor formed in bulk material/substrate) having a channel, which is disposed adjacent to the body and separated from the channel by a gate dielectric. The body region of the transistor is electrically floating in view of the insulation layer (or non-conductive region, for example, in a bulk-type material/substrate) disposed beneath the body region. The state of the memory cell is determined by the concentration of charge within the body region of the SOI transistor.

Data is written into or read from a selected memory cell by applying suitable control signals to a selected word line(s), a selected source line(s) and/or a selected bit line(s). In response, charge carriers are accumulated in or emitted and/or ejected from electrically floating body region wherein the data states are defined by the amount of carriers within electrically floating body region. Notably, the entire contents of the '662 patent, including, for example, the features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are incorporated by reference herein.

Referring to the operations of an N-channel transistor, for example, the memory cell of a DRAM array operates by accumulating in or emitting/ejecting majority carriers (electrons or holes) from body region. In this regard, conventional write techniques may accumulate majority carriers (in this example, “holes”) in body region of memory cells by, for example, impact ionization near source region and/or drain region. In sum, conventional writing programming techniques for memory cells having an N-channel type transistor often provide an excess of majority carriers by impact ionization or by band-to-band tunneling (gate-induced drain leakage (“GIDL”)). The majority carriers may be emitted or ejected from body region by, for example, forward biasing the source/body junction and/or the drain/body junction, such that the majority carrier may be removed via drain side hole removal, source side hole removal, or drain and source hole removal, for example.

Notably, for at least the purposes of this discussion, a logic high data state, or logic “1”, corresponds to, for example, an increased concentration of majority carries in the body region relative to an unprogrammed device and/or a device that is programmed with logic low data state, or logic “0”. In contrast, a logic low data state, or logic “0”, corresponds to, for example, a reduced concentration of majority carriers in the body region relative to a device that is programmed with a logic high data state, or logic “1”. The terms “logic low data state” and “logic 0” may be used interchangeably herein; likewise, the terms “logic high data state” and “logic 1” may be used interchangeably herein.

In one conventional technique, the memory cell is read by applying a small bias to the drain of the transistor as well as a gate bias which is above the threshold voltage of the transistor. In this regard, in the context of memory cells employing N-type transistors, a positive voltage is applied to one or more word lines to enable the reading of the memory cells associated with such word lines. The amount of drain current is determined or affected by the charge stored in the electrically floating body region of the transistor. As such, conventional reading techniques sense the amount of channel current provided/generated in response to the application of a predetermined voltage on the gate of the transistor of the memory cell to determine the state of the memory cell; a floating body memory cell may have two or more different current states corresponding to two or more different logical states (for example, two different current conditions/states corresponding to the two different logical states: “1” and “0”).

Further to writing and reading data to memory cells, data stored in the memory cells is required, under certain circumstances, to be periodically refreshed as a result of leakage current. The refreshing of the memory generally involves periodically reading information or data from an area of the memory (e.g., memory cells), and subsequently rewriting the read information into the same area of memory (e.g., memory cells) from which it was read with no modifications. Conventional refreshing techniques thus use the read and write operations appropriate to the transistor, and perform the read and write during two or more separate clock cycles. The technique used for refreshing data in a dynamic memory can have a large impact on memory performance, including memory availability, die area, and power consumption. Memories are typically and more specifically refreshed by performing a read operation during which data is read from memory cells into sense amps, followed by a write operation during which data is written back into the memory cells.

Conventional solutions to improve memory availability have typically involved increasing the number of sense amps in the memory so more of the memory can be refreshed at the same time. Unfortunately, the addition of more sense amps increases memory die area. Additionally, conventional refresh techniques often lead to relatively large power consumption due to, for example, the separate read and write operations of the refresh. The present inventions, in one aspect, are directed to allowing the refreshing of memory cells in a single cycle.

INCORPORATION BY REFERENCE

Each patent, patent application, and/or publication mentioned in this specification is herein incorporated by reference in its entirety to the same extent as if each individual patent, patent application, and/or publication was specifically and individually indicated to be incorporated by reference.

BRIEF DESCRIPTION OF THE DRAWINGS

In the course of the detailed description to follow, reference will be made to the attached drawings. These drawings show different aspects of the present inventions and, where appropriate, reference numerals illustrating like structures, components, materials and/or elements in different figures are labeled similarly. It is understood that various combinations of the structures, components, materials and/or elements, other than those specifically shown, are contemplated and are within the scope of the present inventions.

Moreover, there are many inventions described and illustrated herein. The present inventions are neither limited to any single aspect nor embodiment thereof, nor to any combinations and/or permutations of such aspects and/or embodiments. Moreover, each of the aspects of the present inventions, and/or embodiments thereof, may be employed alone or in combination with one or more of the other aspects of the present inventions and/or embodiments thereof. For the sake of brevity, many of those permutations and combinations will not be discussed separately herein.

FIG. 1A is a memory cell configured for single-cycle refresh, under an embodiment;

FIG. 1B is a memory cell configured for single-cycle refresh, under an alternative embodiment;

FIG. 2 shows relative magnitudes and timing of control signal application to a floating-body transistor during single-cycle refresh operations, under an embodiment;

FIG. 3 shows relative magnitudes and timing of control signal application to a floating-body transistor during multi-cycle refresh operations, under an embodiment;

FIGS. 4A-4B show various stages of operation of transistor when writing or programming logic “1”, under an embodiment;

FIGS. 5A-5B show various stages of operation of transistor when writing or programming logic “0”, under an embodiment;

FIG. 6 is an example of an operation under which the data state of a memory cell may be read and/or determined by applying control signals having predetermined voltages to gate and source region and drain region of transistor, under an embodiment;

FIG. 7A shows electrically floating body transistor schematically illustrated as including a MOS capacitor “component” and an intrinsic bipolar transistor “component”, under an embodiment;

FIG. 7B is an example characteristic curve of electrically floating body transistor, under an embodiment;

FIG. 8 is a flow diagram for forming a transistor, under an embodiment;

FIGS. 9A and 9B are schematic block diagrams of embodiments of an integrated circuit device including, among other things, a memory cell array, data sense and write circuitry, memory cell selection and control circuitry, according certain aspects of the present inventions; and

FIGS. 10-12 illustrate an embodiment of an exemplary memory array having a plurality of memory cells and employing a separate source line configuration for each row of memory cells, according to certain aspects of the present inventions.

DETAILED DESCRIPTION

There are many inventions described herein as well as many aspects and embodiments of those inventions. In one aspect, the present inventions are directed to a semiconductor device including an electrically floating body. “Electrically floating body” or “floating body” refers to a transistor body which is not coupled to, and is therefore insulated from, power or ground rails within a semiconductor device or integrated circuit (IC) chip. Various levels of charge may therefore accumulate within a floating body of a transistor. Floating-body transistors are a significant characteristic of SOI devices.

In another aspect, the present inventions are directed to techniques to control and/or operate a semiconductor memory cell (and memory cell array having a plurality of such memory cells as well as an integrated circuit device including a memory cell array) having one or more electrically floating body transistors in which an electrical charge is stored in the body region of the electrically floating body transistor. The techniques of the present inventions may employ intrinsic bipolar transistor currents (referred to herein as “source” currents) to control, write, read and/or refresh a data state in such a memory cell. In this regard, the present inventions may employ the intrinsic bipolar source current to control, write, read and/or refresh a data state in/of the electrically floating body transistor of the memory cell.

The present inventions are also directed to semiconductor memory cell, array, circuitry and device to implement such control and operation techniques. Notably, the memory cell and/or memory cell array may comprise a portion of an integrated circuit device, for example, logic device (such as, a microcontroller or microprocessor) or a portion of a memory device (such as, a discrete memory).

FIG. 1A is a memory cell 12 configured for single-cycle refresh, under an embodiment. The refresh operations described herein are also referred to as “single-cycle refresh” operations. The memory cell 12 is configured at least nearly the same as or representative of numerous other memory cells of a memory array (not shown) to which the memory cell 12 may be coupled. The memory cell 12 includes a transistor 14 having gate 16, body region 18, which is configured to be electrically floating, source region 20 and drain region 22. The body region 18 is disposed between source region 20 and drain region 22. Moreover, body region 18 is disposed on or above region 24, which may be an insulation region (for example, in an SOI material/substrate) or non-conductive region (for example, in a bulk-type material/substrate). The insulation or non-conductive region 24 may be disposed on substrate 26.

Data is written into, read from, or refreshed in a selected memory cell 12 by applying suitable control signals to a selected word line(s) 28, a selected source line(s) 30 and/or a selected bit line(s) 32. For example, the gate 16 of a transistor 14 of an embodiment is coupled to a word line 28, the source region 20 is coupled to a source line 30, and the drain region 22 is coupled to a bit line 32. In response to the control signals, charge carriers are accumulated in or emitted and/or ejected from electrically floating body region 18 wherein the data states are defined by the amount of carriers within electrically floating body region 18.

FIG. 1B is a memory cell 12 configured for single-cycle refresh, under an alternative embodiment. The memory cell 12 includes a transistor 14 having gate 16, body region 18, which is configured to be electrically floating, source region 20 and drain region 22. The body region 18 is disposed between drain region 20 and source region 22. Moreover, body region 18 is disposed on or above region 24, which may be an insulation region (for example, in an SOI material/substrate) or non-conductive region (for example, in a bulk-type material/substrate). The insulation or non-conductive region 24 may be disposed on substrate 26.

The description herein describes write, read and refresh operations corresponding to the floating-body transistors provided herein. It is understood that the write and read operations described herein are components of refresh operations, so any description herein of write and/or read operations includes write and/or read operations that are components of the refresh operations provided herein.

Data is written into, read from, or refreshed in a selected memory cell 12 by applying suitable control signals to a selected word line(s) 28, a selected source line(s) 30 and/or a selected bit line(s) 32. For example for FIG. 1B, the gate 16 of a transistor 14 of an embodiment is coupled to a word line 28, the drain region 20 is coupled to a bit line 32, and the source region 22 is coupled to a source line 30. In response to the control signals, charge carriers are accumulated in or emitted and/or ejected from electrically floating body region 18 wherein the data states are defined by the amount of carriers within electrically floating body region 18.

The memory cell 12 of an embodiment generally operates by accumulating in or emitting/ejecting majority carriers (electrons or holes) from body region 18. In this regard, write operations or techniques may accumulate majority carriers (e.g., “holes”) in body region 18 of memory cell transistors by, for example, impact ionization near drain region 20 and/or source region 22, as described in detail herein. During read operations, the majority carriers may be emitted or ejected from body region 18 by, for example, forward biasing the source/body junction and/or the drain/body junction as described in detail herein.

Writing data into a selected memory cell 12 of an embodiment includes applying suitable control signals to a selected word line(s) 28, a selected source line(s) 30 and/or a selected bit line(s) 32, as described in detail herein. As a result of the body region 18 being electrically insulated from the underlying substrate 26 by an insulating layer 24, the control signals result in data being written to the transistor in the form of charge stored in the body region 18. The stored charge may be referred to as “body charge” but is not so limited.

The configuration of the memory cell 12 described herein, which consists essentially of one transistor, is in contrast to body-contacted dynamic random access memory (BCDRAM) cells that include multiple transistors per cell. For example, each BCDRAM cell includes, in addition to a storage transistor, one or more access transistors contacted to a contact of the body region of the storage transistor. The numerous transistors included in the configuration of a BCDRAM cell (an example of which is provided in U.S. Pat. No. 6,111,778) thus makes write and/or read operations different from those described herein for use in the operation of memory cell 12.

Data is read from a memory cell 12 of an embodiment by generally applying suitable control signals to a selected word line(s) 28, a selected source line(s) 30 and/or a selected bit line(s) 32 that cause the body-to-source junction (PN junction) to become forward biased or not depending on data state. This condition precipitates an inherent bipolar current. The total charge of the bipolar current has a magnitude proportional to the charge accumulated on the body region 18 of the transistor multiplied by the current gain (beta value) of the inherent bipolar transistor. The inherent bipolar current is a distorted pulse waveform of relatively short duration. In this manner the effective value of capacitance, in terms of the magnitude of discharge current sensed at a bit line (FIG. 1A-1B, element 32), is enhanced by this parasitic bipolar effect.

FIG. 2 shows relative magnitudes and timing of control signal application to a floating-body transistor 14 during single-cycle refresh operations, under a first embodiment. The one- or single-cycle refresh of an embodiment reads data and writes back either a logic low or logic high data state (as appropriate to the data read) during a single clock cycle. The single-cycle refresh generally saves time and has relatively lower power consumption when compared to the conventional two-cycle refresh. The faster speed and lower power consumption result from the fact that the voltages applied to the source and gate of the transistor during the single-cycle are not returned to hold state values between the read and write operations.

During refresh operations, the floating-body transistor of a second embodiment has the characteristic that, when reading a memory cell previously written to the logic high data state (the body of the memory cell transistor is positively charged), current flows from collector to emitter of the parasitic bipolar transistor. This bipolar current generates electron-hole pairs of which the holes are collected in the floating body of the transistor. In this way, body charge is reinforced or refreshed during a read of a logic high data state. Conversely, during a read of a memory cell previously written to logic low data state, parasitic bipolar current does not flow, electron-hole pairs are not created, and body charge of the transistor is not changed.

Refresh operations of a transistor can also be affected by the hold state of the floating-body transistor. Depending on the transistor gate voltage during the hold state, either logic low data state retention or logic high data state retention is favored during the hold state. Typically gate voltage during hold is chosen so that logic low data and logic high data states have equal retention. In the second embodiment, however, the gate voltage during the hold state is selected so that the logic low data state is favored, and only the logic high data state needs to be refreshed.

The logic high data state is refreshed periodically in the second embodiment by reading the transistor to regenerate body charge as described above. Because it is the read operation that regenerates body charge, a write operation is not necessary. Also, because the read voltages applied to the transistor restore the logic high data state body charge, sense amp circuitry is not required for the refresh technique of the second embodiment.

The single-cycle refresh of the second embodiment accomplishes a refresh operation in one cycle so the refresh is faster and memory availability is higher. Furthermore, as described above, sense amps are not required for refresh using read without write (e.g., refresh of floating-body transistor in logic high data state). This means that entire rows of memory cells in multiple banks can be simultaneously refreshed. In memory array architectures like the DC source line array architecture, for which there are no source line drivers, entire banks of memory cells can be simultaneously refreshed.

Referring to FIGS. 1A, 1B, and 2, the single-cycle refresh of the first embodiment reads data and writes back either a logic low or logic high data state (as appropriate to the data read) during a single clock cycle. The read portion of the refresh is performed during a first portion of the clock cycle and is followed in the same clock cycle by an appropriate write operation. The read operation of the first embodiment applies control signals having predetermined voltages to gate 16 and source region 20 and drain region 22 of transistor 14. As an example, the control signals include a gate voltage of approximately Vg=−0.5v, source voltage of approximately Vs=2.5v and drain voltage of approximately Vd=0v, respectively, but are not so limited.

The write portion of the refresh is performed during a second, remaining, or last portion of the same clock cycle as the read portion. The write operation writes back either a logic low or logic high data state according to the data read during the read portion of the refresh. When the write operation is refreshing a logic high data state, for example, the write operation of the first embodiment applies control signals that include a gate voltage of approximately Vg=0.5v, source voltage of approximately Vs=2.5v and drain voltage of approximately Vd=0v, respectively, but are not so limited. A logic high programming operation of the first embodiment can include a two stage control signal application during which the gate voltage during the write operation is changed from a first voltage level (e.g., Vg=0.5v) to a second voltage level (e.g., Vg=−1.2v), but the embodiment is not so limited.

When the write portion of the refresh operation is refreshing a logic low data state, for example, the write operation of the first embodiment applies control signals that include a gate voltage of approximately Vg=0.5v, source voltage of approximately Vs=2.5v and drain voltage of approximately Vd=0.5v, respectively, but are not so limited. A logic low programming operation of the first embodiment can include a two stage control signal application during which the gate voltage during the write operation is changed from a first voltage level (e.g., Vg=0.5v) to a second voltage level (e.g., Vg=−1.2v), but the embodiment is not so limited.

The voltage levels to implement the refresh operations are merely examples of control signals. Indeed, the indicated voltage levels may be relative or absolute. Alternatively, the voltages indicated may be relative in that each voltage level, for example, may be increased or decreased by a given voltage amount (for example, each of the gate, source, and drain voltage may be increased or decreased by 0.5, 1.0 and 2.0 volts) whether one or more of the voltages (for example, the source, drain or gate voltages) become or are positive and negative.

The single-cycle refresh is in contrast to conventional refresh operations of floating-body transistors. FIG. 3 shows relative magnitudes and timing of control signal application to a floating-body transistor 14 during multi-cycle refresh operations. The multi-cycle refresh operations make use of a read operation applied to the transistor during a first clock cycle, followed by a refresh (write) operation applied to the transistor during a second or subsequent clock cycle. The refresh (write) operation that follows the read includes a write operation that writes either a logic low or logic high data state to the transistor as appropriate to the data read from the transistor during the read operation.

FIG. 3 separately shows bias signals or voltages versus time for each of the read, write logic low (“0”) and write logic high (“1”) operations. The timing and magnitude of these signals are shown as examples only and are not intended to limit the embodiments described herein to the timing and magnitude shown in this figure.

As described herein, the read and write operations of the refresh operation are the same as or similar to independent read and write operations used to program and read the transistor. Consequently, and as an example of read operations used during the single-cycle refresh of an embodiment, FIGS. 4A-4B show operation of transistor 14 when writing or programming a logic “1”, under an embodiment. The transistor 14 of this embodiment is an N-channel or nMOS FET, but is not so limited; transistor 14 may be a P-channel or pMOS FET in an alternative embodiment. The N-channel device includes source 20 and drain 22 regions comprising N+-type material while the body region 18 comprises a P-type material.

As a general example for use with floating-body transistors, a logic “1” programming operation of an embodiment includes a two stage control signal application during which the gate voltage is changed from a first voltage level to a second voltage level. In operation, when writing or programming logic “1”, in one embodiment, control signals having predetermined voltages (e.g., Vg=0.5v, Vs=0v, and Vd=2.5v) are initially applied during stage one to gate 16, source region 20 and drain region 22 (respectively) of transistor 14 of memory cell 12 (FIG. 4A). The stage one control signals may result in an accumulation of majority carriers (not shown) in the electrically floating body 18. As a result of the polarity (e.g., positive) of the control signal applied to the gate with the stage one control signals, any majority carriers that happen to be present in the body region 18 accumulate in the first portion 18-1 of the body 18. The majority carriers may accumulate in an area of the first portion 18-1 under the gate, but are not so limited.

Furthermore, even if an inversion channel were to form in the first portion 18-1 of the body region as a result of the gate voltage, the inversion channel would not form in the second 18-2 and third 18-3 portions of the body region because these regions 18-2/18-3 are not under the gate. Therefore, any inversion channel formed under the embodiments described herein would be “disconnected” from or discontinuous with the source 20 and drain 22 regions.

The stage one control signals also generate or provide a source current in electrically floating body region 18 of transistor 14. More specifically, the potential difference between the source voltage and the drain voltage (e.g., 2.5 volts) is greater than the threshold required to turn on the bipolar transistor. Therefore, source current of the transistor causes or produces impact ionization and/or the avalanche multiplication phenomenon among carriers in the electrically floating body region 18. The impact ionization produces, provides, and/or generates an excess of majority carriers 806 (FIG. 4B) in the electrically floating body region 18 of transistor 14 of memory cell 12 as described above.

Notably, it is preferred that the source current responsible for impact ionization and/or avalanche multiplication in electrically floating body region 18 is initiated or induced by the control signal applied to gate 16 of transistor 14 along with the potential difference between the source 20 and drain 22 regions. Such a control signal may induce channel impact ionization which raises or increases the potential of body region 18 and “turns on”, produces, causes and/or induces a source current in transistor 14. One advantage of the proposed writing/programming technique is that a large amount of the excess majority carriers 806 may be generated and stored in electrically floating body region 18 of transistor 14.

The stage two control signals are subsequently applied to the transistor when writing or programming logic “1” as described above. The stage two control signals are control signals having predetermined voltages (for example, Vg=−1.0v, Vs=0v, and Vd=2.5v) applied to gate 16, source region 20 and drain region 22 (respectively) of transistor 14 of memory cell 12 (FIG. 4B) subsequent to stage one. As a result of the polarity (e.g., negative) of the control signal applied to the gate with the stage two control signals, the majority carriers 806 of the body region 18 accumulate near the surface of the first portion 18-1 of the body region (FIG. 4B). The polarity of the gate signal (e.g., negative) combined with the floating body causes the majority carriers 806 to become trapped or “stored” near the surface of the first portion 18-1 of the body region. In this manner the body region 18 of the transistor “stores” charge (e.g., equivalently, functions like a capacitor). Thus, in this embodiment, the predetermined voltages of the stage one and stage two control signals program or write logic “1” in memory cell 12 via impact ionization and/or avalanche multiplication in electrically floating body region 18.

FIGS. 5A-5B show operation of transistor 14 when writing or programming logic “0”, under an embodiment. As a general example for use with floating-body transistors, a logic “0” programming operation of an embodiment includes a two stage control signal application during which the gate voltage is changed from a first voltage level to a second voltage level. In operation, when writing or programming logic “0”, in one embodiment, control signals having predetermined voltages (for example, Vg=0.5v, Vs=0.5v, and Vd=2.5v) are initially applied during stage one to gate 16, source region 20 and drain region 22 (respectively) of transistor 14 of memory cell 12 (FIG. 5A). The stage one control signals may result in an accumulation of minority carriers (not shown) in the electrically floating body 18. More specifically, as a result of the polarity (e.g., positive) of the control signal applied to the gate with the stage one control signals, any accumulation of minority carriers occurs under the gate 16 in the first portion 18-1 of the body region, in an area that is close to the interface between gate dielectric 32 and electrically floating body 18 as described above. Any minority carriers that accumulate are in the first portion 18-1 of the body region as a result of the gate voltage, and thus do not accumulate in the second 18-2 and third 18-3 portions of the body region. Therefore, the accumulated charge of the body region 18 is discontinuous with the source 20 and drain 22 regions.

The potential difference between the source voltage and the drain voltage (e.g., 2.0 volts) of the stage one control signals, however, is less than the threshold required to turn on transistor 14. Consequently, no impact ionization takes place among carriers in the body region 18 and no bipolar or source current is produced in the electrically floating body region 18. Thus, no excess of majority carriers are generated in the electrically floating body region 18 of transistor 14 of memory cell 12.

The stage two control signals are subsequently applied to the transistor 14 when writing or programming logic “0” as described above. The stage two control signals are control signals having predetermined voltages (for example, Vg=−1.0v, Vs=0.5v, and Vd=2.5v) applied to gate 16, source region 20 and drain region 22 (respectively) of transistor 14 of memory cell 12 (FIG. 5B) subsequent to stage one. The polarity (e.g., negative) of the gate signal may result in any minority carriers that accumulate being removed from electrically floating body region 18 of transistor 14 via one or more of the source region 20 and the drain region 22. Furthermore, the polarity of the gate signal (e.g., negative) causes any minority carriers remaining in the body region 18 to be trapped or “stored” near the surface of the first portion of the body region 18. The result is an absence of excess majority carriers in the body region 18 so that, in this manner, the predetermined voltages of the stage one and stage two control signals program or write logic “0” in memory cell 12.

A logic “0” programming operation of an alternative embodiment includes a two stage control signal application during which the gate voltage is changed from a first voltage level to a second voltage level. In operation, when writing or programming logic “0”, in this alternative embodiment, control signals having predetermined voltages (for example, Vg=0v, Vs=0v, and Vd=0v) are initially applied during stage one to gate 16, source region 20 and drain region 22 (respectively) of transistor 14 of memory cell 12.

The voltage levels described here as control signals to implement the write operations are provided merely as examples, and the embodiments described herein are not limited to these voltage levels. The control signals increase the potential of electrically floating body region 18 which “turns on”, produces, causes and/or induces a source current in the transistor of the memory cell. In the context of a write operation, the source current generates majority carriers in the electrically floating body region which are then stored. In the context of a read operation, the data state may be determined primarily by, sensed substantially using and/or based substantially on the source current that is responsive to the read control signals, as described above, and significantly less by the interface channel current component, which is less significant and/or negligible relative to the bipolar component.

Accordingly, the voltage levels to implement the write operations are merely examples of control signals. Indeed, the indicated voltage levels may be relative or absolute. Alternatively, the voltages indicated may be relative in that each voltage level, for example, may be increased or decreased by a given voltage amount (for example, each of the gate, source, and drain voltage may be increased or decreased by 0.5, 1.0 and 2.0 volts) whether one or more of the voltages (for example, the source, drain or gate voltages) become or are positive and negative.

With reference to FIG. 6, and as a general example for use with floating-body transistors of an embodiment, the data state of memory cell 12 may be read and/or determined by applying control signals having predetermined voltages to gate 16 and source region 20 and drain region 22 of transistor 14 (for example, Vg=−0.5v, Vs=2.5v and Vd=0v, respectively). Such control signals, in combination, induce and/or cause a source current in memory cells 12 that are programmed to logic “1” as described above. As such, sensing circuitry (for example, a cross-coupled sense amplifier), which is coupled to transistor 14 (for example, drain region 22) of memory cell 12, senses the data state using primarily and/or based substantially on the source current. Notably, for those memory cells 12 that are programmed to logic “0”, such control signals induce, cause and/or produce little to no source current (for example, a considerable, substantial or sufficiently measurable source current).

Thus, in response to read control signals, electrically floating body transistor 14 generates a source current which is representative of the data state of memory cell 12. Where the data state is logic high or logic “1”, electrically floating body transistor 14 provides a substantially greater source current than where the data state is logic low or logic “0”. Electrically floating body transistor 14 may provide little to no source current when the data state is logic low or logic “0”. As discussed in more detail below, data sensing circuitry determines the data state of the memory cell based substantially on the source current induced, caused and/or produced in response to the read control signals.

The voltage levels described here as control signals to implement the read operations are provided merely as examples, and the embodiments described herein are not limited to these voltage levels. The indicated voltage levels may be relative or absolute. Alternatively, the voltages indicated may be relative in that each voltage level, for example, may be increased or decreased by a given voltage amount (for example, each voltage may be increased or decreased by 0.5, 1.0 and 2.0 volts) whether one or more of the voltages (for example, the source, drain or gate voltages) become or are positive and negative.

FIG. 7A shows electrically floating body transistor 14 schematically illustrated as including a MOS capacitor “component” and an intrinsic bipolar transistor “component”, under an embodiment. In one aspect, the present inventions employ the intrinsic bipolar transistor “component” to program/write as well as read memory cell 12. In this regard, the intrinsic bipolar transistor generates and/or produces a source or bipolar transistor current which is employed to program/write the data state in memory cell 12 and read the data state of memory cell 12. Notably, in this example embodiment, electrically floating body transistor 14 is an N-channel device. As such, majority carriers 34 are “holes”.

The bipolar transistor 14 of an embodiment has a floating body, meaning the potential is not fixed or “floating”. The potential for example depends on the charge at the gate. A conventional bipolar transistor requires each of base current, emitter current, and collector current for proper operation. Any base of the transistor 14 in this embodiment, however, is floating and not fixed because there is no base contact as found in conventional bipolar FETs; the current in this transistor is therefore referred to herein as a “source” current produced by impact ionization in the body region as described below.

FIG. 7B is an example characteristic curve of electrically floating body transistor 14, under an embodiment. The characteristic curve shows a significant increase in source current (e.g., “log I”) at and above a specific threshold value of the potential difference between applied source voltage and applied drain voltage (“source-drain potential difference”). The reason for this is that a voltage differential at or above a certain threshold generates a high electric field in the body region. The high electric field results in impact ionization in the first portion 18-1 of the body region 18, a process during which electrons or particles with enough energy generate majority carriers i.e. holes. The impact ionization drives majority carriers to the body region, which increases the body potential, while any minority carriers flow to the drain (or source) region. The increased body potential results in an increase in source current in the body region; thus, the excess majority carriers of the body region generate source current of transistor 14 of an embodiment.

FIG. 8 is a flow diagram for forming transistor 14, under an embodiment. Transistor 14 is formed, generally, by forming 1002 a semiconductor on an insulator. An insulating layer and a gate is formed 1004 over a first portion of the semiconductor. Spacers are formed 1006 over a second portion and a third portion of the semiconductor, and the spacers adjoin the insulating layer. The first portion, second portion, and third portion of the semiconductor collectively form the floating body region. Formation of transistor 14 continues by forming 1008 a source region through implantation of an impurity into a fourth portion of the semiconductor after forming the spacers. The fourth portion of the semiconductor is adjacent the second portion. A drain region is also formed 1008 by implanting the impurity into a fifth portion of the semiconductor after forming the spacers. The fifth portion of the semiconductor is adjacent the third portion.

As mentioned above, the embodiments described herein may be implemented in an IC device (for example, a discrete memory device or a device having embedded memory) including a memory array having a plurality of memory cells arranged in a plurality of rows and columns wherein each memory cell includes an electrically floating body transistor. The memory arrays may comprise N-channel, P-channel and/or both types of transistors. Indeed, circuitry that is peripheral to the memory array (for example, data sense circuitry (for example, sense amplifiers or comparators), memory cell selection and control circuitry (for example, word line and/or source line drivers), as well as row and column address decoders) may include P-channel and/or N-channel type transistors.

For example, with reference to FIGS. 9A and 9B, the integrated circuit device may include array 10, having a plurality of memory cells 12, data write and sense circuitry 36, and memory cell selection and control circuitry 38. The data write and sense circuitry 36 reads data from and writes data to selected memory cells 12. In one embodiment, data write and sense circuitry 36 includes one or more data sense amplifiers. Each data sense amplifier receives at least one bit line 32 and an output of reference generator circuitry (for example, a current or voltage reference signal). In one embodiment, the data sense amplifier may be a cross-coupled type sense amplifier as described and illustrated in the Non-Provisional U.S. patent application Ser. No. 11/299,590 (U.S. Patent Application Publication US 2006/0126374), filed by Waller and Carman, on Dec. 12, 2005, and entitled “Sense Amplifier Circuitry and Architecture to Write Data into and/or Read Data from Memory Cells”, the application being incorporated herein by reference in its entirety) to sense the data state stored in memory cell 12 and/or write-back data into memory cell 12.

The data sense amplifier may employ voltage and/or current sensing circuitry and/or techniques. In the context of current sensing, a current sense amplifier may compare the current from the selected memory cell to a reference current, for example, the current of one or more reference cells. From that comparison, it may be determined whether memory cell 12 contained logic high (relatively more majority carries 34 contained within body region 18) or logic low data state (relatively less majority carries 28 contained within body region 18). Notably, the present inventions may employ any type or form of data write and sense circuitry 36 (including one or more sense amplifiers, using voltage or current sensing techniques, to sense the data state stored in memory cell 12) to read the data stored in memory cells 12, write data in memory cells 12 and/or refresh the data stored in memory cells 12.

Memory cell selection and control circuitry 38 selects and/or enables one or more predetermined memory cells 12 to facilitate reading data from, writing data to and/or refreshing data in the memory cells 12 by applying a control signal on one or more word lines 28. The memory cell selection and control circuitry 38 may generate such control signals using address data, for example, row address data. Indeed, memory cell selection and control circuitry 38 may include a conventional word line decoder and/or driver. There are many different control/selection techniques (and circuitry) to implement the memory cell selection technique. Such techniques, and circuitry, are well known to those skilled in the art. All such control/selection techniques, and circuitry, whether now known or later developed, are intended to fall within the scope of the present embodiments.

The present inventions may be implemented in any architecture, layout, and/or configuration comprising memory cells having electrically floating body transistors. For example, in one embodiment, memory array 10 including a plurality of memory cells 12 having a separate source line for each row of memory cells (a row of memory cells includes a common word line connected to the gates of each memory cell of the row). The memory array 10 may employ one or more of the example programming, reading, refreshing and/or holding techniques described above.

In one embodiment, the present inventions are implemented in conjunction with a two step write operation whereby all the memory cells of a given row are written to a predetermined data state by first executing a “clear” operation, whereby all of the memory cells of the given row are written or programmed to logic “0”, and thereafter selective memory cells of the row are selectively write operation to the predetermined data state (here logic “1”). The present inventions may also be implemented in conjunction with a one step write operation whereby selective memory cells of the selected row are selectively written or programmed to either logic “1” or logic “0” without first implementing a “clear” operation.

With reference to FIGS. 10 and 11, memory cells 12 may be programmed using the two step operation wherein a given row of memory cells are written to a first predetermined data state by first executing a “clear” operation (which, in this example embodiment, all of the memory cells of the given row are written or programmed to logic “0”) and thereafter selected memory cells are written to a second predetermined data state (i.e., a selective write operation to the second predetermined data state). The “clear” operation may be performed by writing or programming each memory cell of the given row to a first predetermined data state (in this example embodiment the first predetermined data state is logic “0”) using the inventive technique described above.

In particular, transistor of each memory cell 12 of a given row (for example, memory cells 12 a-12 d) is controlled to store a logic “0”. In this regard, stage one and stage two control signals to implement a clear operation as described above are applied to the gate, the source region and the drain region of the transistor of memory cells 12 a-12 d. In response, the same logic state (for example, logic low or logic “0”) is stored in memory cells 12 a-12 d and the state of memory cells 12 a-12 d are “cleared”.

Thereafter, selected memory cells of the given row may be programmed to the second predetermined logic state. In this regard, the transistors of certain memory cells of a given row are written to the second predetermined logic state in order to store the second predetermined logic state in memory cells. For example, with reference to FIG. 11, memory cells 12 b and 12 c are programmed to logic high or logic “1” by applying (i) 0.5v to the gate (via word line 28 _(i)), (ii) 0v to the source region (via source line 30 _(i)), and (iii) 2.5v to the drain region (via bit line 32 _(j)+1 and 32 _(j+2)), followed by application of −1.0v to the gate (via word line 28 _(i)). In particular, such control signals generate or provide an excess of majority carriers in the electrically floating body region of the transistor of memory cells 12 b and 12 c which corresponds to logic high or logic “1”.

As mentioned above, it is preferred that the source current responsible for impact ionization and/or avalanche multiplication in the floating body is initiated or induced by the control signal (control pulse) applied to the gate of the transistor. Such a signal/pulse may induce the channel impact ionization which raises or increases the potential of the electrically floating body region of the transistor of memory cells 12 b and 12 c and “turns-on” and/or produces a source current in transistor 14. One advantage of the proposed method is that a large amount of the excess majority carriers may be generated and stored in the electrically floating body region of the transistor of memory cells 12 b and 12 c.

Notably, in this example embodiment, memory cells 12 a and 12 d are maintained at logic low (or logic “0”) by applying an inhibit control signal to the drain region of each memory cell 12 a and 12 d. For example, applying 0v to the drain regions of memory cells 12 a and 12 d (via bit lines 32 _(j) and 32 _(j+4)) inhibits writing logic high or logic “1” into memory cells 12 a and 12 d during the selective write operation for memory cells 12 b and 12 c.

A “holding” operation or condition may be used for the other memory cells in memory cell array 10 to minimize and/or reduce the impact of the write operation for memory cells 12 a-12 d connected to word line 28 _(i). In one embodiment, a holding voltage is applied to the gates of the transistors of other memory cells of memory cell array 10 (for example, each memory cell connected to word lines 28 _(i+1), 28 _(i+2), 28 _(i+3), and 28 _(i+4)). In one example embodiment, a holding voltage approximately in a range of −0.8 volts to −1.6 volts (e.g., −1.2 volts) is applied to the gate of each transistor of the memory cells connected to word lines 28 _(i+1), 28 _(i+2), 28 _(i+3), and 28 _(i+4). In this way, the impact of the write operation of memory cells 12 a-12 d (which are connected to word line 28 _(i)) on the other memory cells of memory cell array 10 is minimized and/or reduced.

A selected row of memory cells may be read by applying read control signals to the associated word line 28 and associated source lines 30 and sensing a signal (voltage and/or current) on associated bit lines 32. In one example embodiment, with reference to FIG. 12, memory cells 12 a-12 d are read by applying (i) 0v to the gate (via word line 28 _(i)), (ii) 0v to the source region (via source line 30 _(i)) and (iii) a voltage approximately in a range of one (1) volt to 2.2 volts to the drain region (via bit line 32 _(j+1) and 32 _(j+2)). The data write and sense circuitry 36 reads the data state of the memory cells 12 a-12 d by sensing the response to the applied read control signals. In response to the read control signals, memory cells 12 a-12 d generate a source current spike or pulse which is representative of the data state of memory cells 12 a-12 d, as described above. In this example, memory cells 12 b and 12 c (which were earlier programmed to logic “1”), in response to the read control signals, generate a source current spike which is considerably larger than any channel current. In contrast, in memory cells 12 a and 12 d (which were earlier programmed to logic “0”), the control signals induce, cause and/or produce little to no source current (for example, a considerable, substantial or sufficiently measurable source current). The sense circuitry 36 senses the data state using primarily and/or based substantially on the source current.

Thus, in response to read control signals, the electrically floating body transistor of each memory cell 12 a-12 d generates a source current spike which is representative of the data state stored therein. The data sensing circuitry in data write and sense circuitry 36 determines the data state of memory cells 12 a-12 d based substantially on the source current induced, caused and/or produced in response to the read control signals. Notably, as mentioned above, a read operation may be performed by applying other control signaling techniques.

Again, it may be advantageous to employ a “holding” operation or condition for the other memory cells in memory cell array 10 to minimize and/or reduce the impact of the read operation of memory cells 12 a-12 d. With continued reference to FIG. 12, in one embodiment, a holding voltage is applied to the gates of the transistors of other memory cells of memory cell array 10 (for example, each memory cell connected to word lines 28 _(i+1), 28 _(i+2), 28 _(i+3), and 28 _(i+4)). In one example embodiment, a holding voltage approximately in a range of −0.8 volts to −1.6 volts (e.g., −1.2 volts) is applied to the gate of each transistor of the memory cells connected to word lines 28 _(i+1), 28 _(i+2), 28 _(i+3), and 28 _(i+4). In this way, the impact of the read operation of memory cells 12 a-12 d (which are connected to word line 28 _(i)) on the other memory cells of memory cell array 10 is minimized and/or reduced.

The programming, reading, and refreshing techniques described herein may be used in conjunction with a plurality of memory cells arranged in an array of memory cells. A memory array implementing the structure and techniques of the present inventions may be controlled and configured including a plurality of memory cells having a separate source line for each row of memory cells (a row of memory cells includes a common word line). The memory array may use any of the example programming, reading, refreshing, and/or holding techniques described herein. The memory arrays may comprise N-channel, P-channel and/or both types of transistors. Circuitry that is peripheral to the memory array (for example, sense amplifiers or comparators, row and column address decoders, as well as line drivers (not illustrated herein)) may include P-channel and/or N-channel type transistors. Where P-channel type transistors are employed as memory cells in the memory array(s), suitable write and read voltages (for example, negative voltages) are well known to those skilled in the art in light of this disclosure.

The present inventions may be implemented in any electrically floating body memory cell and memory cell array. For example, in certain aspects, the present inventions are directed to a memory array, having a plurality of memory cells each including an electrically floating body transistor, and/or technique of programming data into and/or reading data from one or more memory cells of such a memory cell array. In this aspect of the inventions, the data states of adjacent memory cells and/or memory cells that share a word line may or may not be individually programmed.

With reference to FIGS. 9A and 9B, memory array 10 may comprise a plurality of memory cells 12 of N-channel type, P-channel type and/or both types of electrically floating body transistors. The memory array 10 includes a plurality of rows and columns (for example, in a matrix form) of memory cells 12.

The circuitry which is peripheral to memory array 10 (for example, data write and sense circuitry 36 (such as, for example, sense amplifiers or comparators), memory cell selection and control circuitry 38 (such as, for example, address decoders and word line drivers)) may include P-channel type and/or N-channel type transistors. Where N-channel type transistors or P-channel type transistors are employed as memory cells 12 in memory array(s) 10, suitable write voltages are known to those skilled in the art.

As mentioned above, memory cells 12 (having electrically floating body transistor 14) and memory cell array 10 of the present inventions may be implemented in an integrated circuit device having a memory portion and a logic portion (see, for example, FIG. 9A), or an integrated circuit device that is primarily a memory device (see, for example, FIG. 9B). Indeed, the present inventions may be implemented in any device having one or more memory cells 12 (having electrically floating body transistors) and/or memory cell arrays 10. For example, with reference to FIG. 9A, an integrated circuit device may include array 10, having a plurality of memory cells 12 (having electrically floating body transistors), data write and sense circuitry, and memory cell selection and control circuitry (not illustrated in detail). The data write and sense circuitry writes data into and senses the data state of one or more memory cells. The memory cell selection and control circuitry selects and/or enables one or more predetermined memory cells 12 to be read by data sense circuitry during a read operation.

For example, the electrically floating body transistor, which programmed (written to), read, refreshed, and/or controlled using the techniques of the present inventions, may be employed in any electrically floating body memory cell, and/or memory cell array architecture, layout, structure and/or configuration employing such electrically floating body memory cells. In this regard, an electrically floating body transistor, which state is read using the techniques of the present inventions, may be implemented in the memory cell, architecture, layout, structure and/or configuration described and illustrated in the following non-provisional U.S. patent applications:

(1) application Ser. No. 10/450,238, which was filed by Fazan et al. on Jun. 10, 2003 and entitled “Semiconductor Device” (now U.S. Pat. No. 6,969,662);

(2) application Ser. No. 10/487,157, which was filed by Fazan et al. on Feb. 18, 2004 and entitled “Semiconductor Device” (U.S. Patent Application Publication No. 2004/0238890);

(3) application Ser. No. 10/829,877, which was filed by Ferrant et al. on Apr. 22, 2004 and entitled “Semiconductor Memory Cell, Array, Architecture and Device, and Method of Operating Same” (U.S. Patent Application Publication No. 2005/0013163);

(4) application Ser. No. 10/840,009, which was filed by Ferrant et al. on May 6, 2004 and entitled “Semiconductor Memory Device and Method of Operating Same” (U.S. Patent Application Publication No. 2004/0228168); and

(5) application Ser. No. 10/941,692, which was filed by Fazan et al. on Sep. 15, 2004 and entitled “Low Power Programming Technique for a One Transistor SOI Memory Device & Asymmetrical Electrically Floating Body Memory Device, and Method of Manufacturing Same” (U.S. Patent Application Publication No. 2005/0063224).

Notably, the memory cells may be controlled (for example, programmed or read) using any of the control circuitry described and illustrated in the above-referenced five (5) U.S. patent applications. For the sake of brevity, those discussions will not be repeated; such control circuitry is incorporated herein by reference. Indeed, all memory cell selection and control circuitry for programming, reading, refreshing, controlling and/or operating memory cells including electrically floating body transistors, whether now known or later developed, are intended to fall within the scope of the present inventions.

Moreover, the data write and data sense circuitry may include a sense amplifier (not illustrated in detail herein) to read the data stored in memory cells 12. The sense amplifier may sense the data state stored in memory cell 12 using voltage or current sensing circuitry and/or techniques. In the context of a current sense amplifier, the current sense amplifier may compare the cell current to a reference current, for example, the current of a reference cell (not illustrated). From that comparison, it may be determined whether memory cell 12 contained logic high (relatively more majority carriers 34 contained within body region 18) or logic low data state (relatively less majority carriers 34 contained within body region 18). Such circuitry and configurations thereof are well known in the art.

In addition, the present inventions may employ the reference generation techniques (used in conjunction with the data sense circuitry for the read operation) described and illustrated in U.S. Provisional Patent Application Ser. No. 60/718,417, which was filed by Bauser on Sep. 19, 2005, and entitled “Method and Circuitry to Generate a Reference Current for Reading a Memory Cell Having an Electrically Floating Body Transistor, and Device Implementing Same”. The entire contents of the U.S. Provisional Patent Application Ser. No. 60/718,417 are incorporated herein by reference. Further, the present inventions may also employ the read circuitry and techniques described and illustrated in U.S. patent application Ser. No. 10/840,902, which was filed by Portmann et al. on May 7, 2004, and entitled “Reference Current Generator, and Method of Programming, Adjusting and/or Operating Same” (now U.S. Pat. No. 6,912,150). The contents of U.S. Provisional Patent Application Ser. No. 60/718,417 and U.S. Pat. No. 6,912,150 are hereby incorporated by reference herein.

It should be further noted that while each memory cell 12 in the example embodiments (described above) includes one transistor 14, memory cell 12 may include two transistors, as described and illustrated in application Ser. No. 10/829,877, which was filed by Ferrant et al. on Apr. 22, 2004 and entitled “Semiconductor Memory Cell, Array, Architecture and Device, and Method of Operating Same” (U.S. Patent Application Publication No. 2005/0013163). The contents of U.S. Patent Application Publication No. 2005/0013163 are hereby incorporated by reference herein

The electrically floating memory cells, transistors and/or memory array(s) may be fabricated using well known techniques and/or materials. Indeed, any fabrication technique and/or material, whether now known or later developed, may be employed to fabricate the electrically floating memory cells, transistors and/or memory array(s). For example, the present inventions may employ silicon, germanium, silicon/germanium, gallium arsenide or any other semiconductor material (whether bulk-type or SOI) in which transistors may be formed. As such, the electrically floating memory cells may be disposed on or in (collectively “on”) SOI-type substrate or a bulk-type substrate.

Indeed, the electrically floating transistors, memory cells, and/or memory array(s) may employ the techniques described and illustrated in non-provisional patent application entitled “Integrated Circuit Device, and Method of Fabricating Same”, which was filed on Jul. 2, 2004, by Fazan, Ser. No. 10/884,481 (U.S. Patent Application Publication No. 2005/0017240), provisional patent application entitled “One Transistor Memory Cell having Mechanically Strained Electrically Floating Body Region, and Method of Operating Same”, which was filed on Oct. 19, 2005, Ser. No. 60/728,060, by Bassin, and/or provisional patent application entitled “Memory Cell, Array and Device, and Method of Operating Same”, which was filed on Oct. 19, 2005, Ser. No. 60/728,061, by Okhonin et al. (hereinafter collectively “Integrated Circuit Device Patent Applications”). The contents of the Integrated Circuit Device Patent Applications are hereby incorporated by reference herein.

Memory array 10 (including SOI memory transistors) further may be integrated with SOI logic transistors, as described and illustrated in the Integrated Circuit Device Patent Applications. For example, in one embodiment, an integrated circuit device includes memory section (having, for example, partially depleted (PD) or fully depleted (FD) SOI memory transistors 14) and logic section (having, for example, high performance transistors, multiple gate transistors, and/or non-high performance transistors (for example, single gate transistors that do not possess the performance characteristics of high performance transistors).

Further, memory array(s) 10 may comprise N-channel, P-channel and/or both types of transistors, as well as partially depleted and/or fully depleted type transistors. For example, circuitry that is peripheral to the memory array (for example, sense amplifiers or comparators, row and column address decoders, as well as line drivers (not illustrated herein)) may include FD-type transistors (whether P-channel and/or N-channel type). Alternatively, such circuitry may include PD-type transistors (whether P-channel and/or N-channel type). There are many techniques to integrate both PD and/or FD-type transistors on the same substrate (see, for example, application Ser. No. 10/487,157, which was filed by Fazan et al. on Feb. 18, 2004 and entitled “Semiconductor Device” (U.S. Patent Application Publication No. 2004/0238890)). All such techniques, whether now known or later developed, are intended to fall within the scope of the present inventions. Where P-channel type transistors are employed as memory cells 12 in the memory array(s), suitable write and read voltages (for example, negative voltages) are well known to those skilled in the art in light of this disclosure.

Notably, electrically floating body transistor 14 may be a symmetrical or non-symmetrical device. Where transistor 14 is symmetrical, the source and drain regions are essentially interchangeable. However, where transistor 14 is a non-symmetrical device, the source or drain regions of transistor 14 have different electrical, physical, doping concentration and/or doping profile characteristics. As such, the source or drain regions of a non-symmetrical device are typically not interchangeable. This notwithstanding, the drain region of the electrically floating N-channel transistor of the memory cell (whether the source and drain regions are interchangeable or not) is that region of the transistor that is connected to the bit line/sense amplifier.

There are many inventions described and illustrated herein. While certain embodiments, features, attributes and advantages of the inventions have been described and illustrated, it should be understood that many others, as well as different and/or similar embodiments, features, attributes and advantages of the present inventions, are apparent from the description and illustrations. As such, the embodiments, features, attributes and advantages of the inventions described and illustrated herein are not exhaustive and it should be understood that such other, similar, as well as different, embodiments, features, attributes and advantages of the present inventions are within the scope of the present inventions.

As mentioned above, the illustrated/example voltage levels to implement the read and write operations are merely examples. The indicated voltage levels may be relative or absolute. Alternatively, the voltages indicated may be relative in that each voltage level, for example, may be increased or decreased by a given voltage amount (for example, each voltage may be increased or decreased by 0.1, 0.15, 0.25, 0.5, 1 volt) whether one or more of the voltages (for example, the source, drain or gate voltages) become or are positive and negative.

The illustrated/example voltage levels and timing to implement the write and read operations are merely examples. In this regard, in certain embodiments, the control signals increase the potential of electrically floating body region of the transistor of the memory cell which “turns on” or produces a source current in the transistor. In the context of a write operation, the source current generates majority carriers in the electrically floating body region which are then stored. In the context of a read operation, the data state may be determined primarily by, sensed substantially using and/or based substantially on the source current that is responsive to the read control signals and significantly less by the interface channel current component, which is less significant and/or negligible relatively to the bipolar component.

Aspects of the present inventions described herein, and/or embodiments thereof, may include an integrated circuit (IC) device. The IC device of an embodiment comprises a memory cell including a transistor. The transistor of an embodiment includes a gate, a body region configured to be electrically floating, and a source region and a drain region adjacent the body region. The IC device of an embodiment comprises refresh circuitry coupled to the memory cell. The refresh circuitry of an embodiment is configured to refresh data of the transistor by sequentially applying to the transistor, during a single clock cycle, read control signals and one of first write control signals and second write control signals.

The refresh circuitry of an embodiment is configured to refresh data of the transistor by applying to the transistor voltage levels substantially the same as read control signals.

The read control signals of an embodiment include a first gate signal applied to a gate of the transistor and a first potential difference applied between a source and a drain of the transistor. The first gate signal of an embodiment includes a voltage approximately in a range of −1.2 volts to zero (0) volts.

The refresh circuitry of an embodiment is configured to apply the first write control signals to the transistor when detecting a logic high data state in the transistor in response to the applying of the read control signals.

The refresh circuitry of an embodiment is configured to apply the second write control signals to the transistor when detecting a logic low data state in the transistor in response to the applying of the read control signals.

The first write control signals and second write control signals of an embodiment include a second gate signal applied to the gate.

The second gate signal of an embodiment includes a voltage approximately in a range of zero (0) volts to one (1) volt.

The first write control signals of an embodiment include signals having a second potential difference applied between a source and a drain of the transistor.

The second potential difference of an embodiment is configured to refresh a logic high data state in the transistor. The second potential difference of an embodiment is greater than a threshold at which current flows in the body region of the transistor. The second write control signals of an embodiment include signals having a third potential difference applied between a source and a drain of the transistor. The third potential difference of an embodiment is configured to refresh a logic low data state in the transistor. The third potential difference of an embodiment is less than a threshold at which current flows in the body region of the transistor.

The first write control signals of an embodiment include signals having a second potential difference applied between a source and a drain of the transistor. The second write control signals of an embodiment include signals having a third potential difference applied between the source and the drain. The second potential difference of an embodiment is greater than the third potential difference.

The body region of the transistor of an embodiment functions as an inherent bipolar transistor.

The integrated circuit device of an embodiment includes data sense circuitry coupled to the memory cell. The data sense circuitry of an embodiment includes a read-word line coupled to the gate and a read-bit output coupled to the source region or the drain region.

The body region of an embodiment stores a data bit in the form of a charge accumulated in the body region. In response to the read control signals, the transistor of an embodiment delivers the data bit onto the read-bit line by discharging the body region in response to a shifting voltage level on the read-word line. The shifting voltage level on the read-word line of an embodiment provides a gate-to-source voltage sufficient to cause read-bit line charging or lack of charging depending on data state. The discharging of an embodiment provides a read current at the read-bit line that is proportional to the current gain of the transistor multiplied by the charge.

The data sense circuitry of an embodiment determines a data state of the memory cell at least substantially based on the read current.

The transistor of an embodiment delivers the data bit onto the read-bit line by discharging the body region in response to a shifting voltage level on a read-source line coupled to the source region or the drain region.

The gate of the transistor of an embodiment is disposed over a first portion of the body region.

The source region of the transistor of an embodiment adjoins a second portion of the body region that is adjacent the first portion and separates the source region from the first portion.

The drain region of the transistor of an embodiment adjoins a third portion of the body region that is adjacent the first portion and separates the drain region from the first portion.

The integrated circuit device of an embodiment includes a first voltage coupled to the gate. The first voltage of an embodiment may cause minority carriers to accumulate in the first portion of the body region.

The minority carriers accumulate in the transistor of an embodiment at a surface region of the first portion of body region that is juxtaposed or near a gate dielectric which is disposed between the gate and the first portion of the body region.

A region of the transistor of an embodiment that includes the minority carriers is disconnected from the source region by the second portion of the body region.

A region of the transistor of an embodiment that includes the minority carriers is disconnected from the drain region by the third portion of the body region.

The integrated circuit device of an embodiment includes a first potential difference coupled between the source and the drain. The first potential difference of an embodiment is greater than a threshold above which bipolar current is generated in the body. The first potential difference of an embodiment generates bipolar current in the body region as a result of impact ionization due to the presence of minority carriers in the body region.

The integrated circuit device of an embodiment includes a first potential difference coupled between the source and the drain. The first potential difference of an embodiment is less than a threshold above which bipolar current is generated in the body.

The integrated circuit device of an embodiment includes a second voltage coupled to the gate after and instead of the first voltage. The second voltage of an embodiment is greater than a threshold which causes an accumulation of minority carriers in the first portion of the body region. The minority carriers of the transistor of an embodiment result in the first data state which is representative of a first charge in the body region.

The integrated circuit device of an embodiment includes a second voltage coupled to the gate after and instead of the first voltage. The second voltage of an embodiment is less than a threshold which causes an accumulation of minority carriers in the first portion of the body region.

One or more of the source region and the drain region of the transistor of an embodiment include a doped region shaped so that a farthermost boundary of the doped region is separated from a portion of the body region underlying the gate.

The body region of the transistor of an embodiment includes a first type of semiconductor material and the source region and drain region include a second type of semiconductor material.

The source region of the transistor of an embodiment includes a lightly doped region.

The source region of the transistor of an embodiment includes a highly doped region.

The source region of the transistor of an embodiment includes a lightly doped region and a highly doped region.

The drain region of the transistor of an embodiment includes a lightly doped region.

The drain region of the transistor of an embodiment includes a highly doped region.

The drain region of the transistor of an embodiment includes a lightly doped region and a highly doped region.

Aspects of the present inventions described herein, and/or embodiments thereof, may include an integrated circuit device. The IC device of an embodiment includes a memory cell including a transistor, the transistor comprising a gate, a body region configured to be electrically floating, and a source region and a drain region adjacent the body region. The IC device of an embodiment includes refresh circuitry coupled to the memory cell. The refresh circuitry of an embodiment is configured to refresh data of the transistor by sequentially applying to the transistor, during a single clock cycle, read control signals and one of first write control signals and second write control signals.

Aspects of the present inventions described herein, and/or embodiments thereof, may include an integrated circuit device. The IC device of an embodiment comprises a memory cell consisting essentially of one transistor. The transistor of an embodiment comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. The IC device of an embodiment comprises refresh circuitry coupled to the memory cell. The refresh circuitry of an embodiment is configured to refresh data of the transistor by applying to the transistor, during a single clock cycle, read control signals followed by write control signals.

The read control signals of an embodiment include a first gate signal applied to a gate of the transistor and a first potential difference applied between a source and a drain of the transistor. The first gate signal of an embodiment includes a voltage approximately in a range of −1.2 volts to zero (0) volts.

The write control signals of an embodiment comprise one of first write control signals and second write control signals. The refresh circuitry of an embodiment is configured to apply the first write control signals to the transistor when detecting a logic high data state in the transistor in response to the applying of the read control signals. The refresh circuitry of an embodiment is configured to apply the second write control signals to the transistor when detecting a logic low data state in the transistor in response to the applying of the read control signals.

The first write control signals and second write control signals of an embodiment include a second gate signal applied to the gate. The second gate signal of an embodiment includes a voltage approximately in a range of zero (0) volts to one (1) volt.

The first write control signals of an embodiment include signals having a second potential difference applied between a source and a drain of the transistor. The second potential difference of an embodiment is configured to refresh a logic high data state in the transistor. The second potential difference of an embodiment is greater than a threshold at which current flows in the body region of the transistor.

The second write control signals of an embodiment include signals having a third potential difference applied between a source and a drain of the transistor. The third potential difference of an embodiment is configured to refresh a logic low data state in the transistor. The third potential difference of an embodiment is less than a threshold at which current flows in the body region of the transistor.

The first write control signals of an embodiment include signals having a second potential difference applied between a source and a drain of the transistor. The second write control signals of an embodiment include signals having a third potential difference applied between the source and the drain, wherein the second potential difference is greater than the third potential difference.

Aspects of the present inventions described herein, and/or embodiments thereof, may include a method for refreshing a memory cell, the memory cell comprising a transistor configured to include a floating body. The method of an embodiment comprises sequentially applying read control signals and refresh control signals to the transistor during a single clock cycle. The refresh control signals of an embodiment comprise one of first write control signals to refresh a first data state and second write control signals to refresh a second data state.

The method of an embodiment comprises selecting one of the first and the second write control signals in response to a data state detected in the transistor during the applying of the read control signals.

The applying of the read control signals of an embodiment comprises applying a first gate signal to a gate of the transistor. The applying of the read control signals of an embodiment comprises applying a source signal to a source of the transistor and a drain signal to a drain of the transistor. A first potential difference is applied between the source and the drain of the transistor of an embodiment.

The applying of the refresh control signals of an embodiment comprises applying a second gate signal to a gate of the transistor.

The method of an embodiment comprises detecting a logic high data state in the floating body in response to the applying of the read control signals. The first write control signals of an embodiment are configured to refresh a logic high data state in the transistor. The applying of the first write control signals of an embodiment comprises generating a second potential difference between a source and a drain of the transistor. The second potential difference of an embodiment is greater than a threshold at which current flows in the transistor.

The method of an embodiment comprises detecting a logic low data state in the transistor. The second write control signals of an embodiment are configured to refresh a logic low data state in the transistor. The applying of the second write control signals of an embodiment comprises generating a third potential difference between a source and a drain of the transistor. The third potential difference of an embodiment is less than a threshold at which current flows in the transistor.

Aspects of the present inventions described herein, and/or embodiments thereof, may include a method for refreshing a memory cell. The method for refreshing a memory cell of an embodiment comprises applying read control signals to a transistor during a clock cycle. The read control signals of an embodiment include a first gate signal applied to a gate of the transistor and a first potential difference applied between a source and a drain of the transistor. A body region of the transistor of an embodiment is configured to be electrically floating. The method for refreshing a memory cell of an embodiment comprises applying write control signals to the transistor during the clock cycle and following the read control signals. The write control signals of an embodiment include a second gate signal applied to the gate and a second or third potential difference applied between a source and a drain of the transistor depending on data state detected in the transistor during the applying of the read control signals.

The method for refreshing a memory cell of an embodiment comprises detecting a logic high data state in the body region in response to the read control signals. The second potential difference of an embodiment is configured to refresh the logic high data state. The second potential difference of an embodiment is greater than a threshold at which current flows in the body region.

The method for refreshing a memory cell of an embodiment comprises detecting a logic low data state in the body region. The third potential difference of an embodiment is configured to refresh the logic low data state. The third potential difference of an embodiment is less than a threshold at which current flows in the body region.

As mentioned above, each of the aspects of the present inventions, and/or embodiments thereof, may be employed alone or in combination with one or more of such aspects and/or embodiments. For the sake of brevity, those permutations and combinations will not be discussed separately herein. As such, the present inventions are neither limited to any single aspect (nor embodiment thereof), nor to any combinations and/or permutations of such aspects and/or embodiments.

Moreover, the above embodiments of the present inventions are merely example embodiments. They are not intended to be exhaustive or to limit the inventions to the precise forms, techniques, materials and/or configurations disclosed. Many modifications and variations are possible in light of the above teaching. It is to be understood that other embodiments may be utilized and operational changes may be made without departing from the scope of the present inventions. As such, the foregoing description of the example embodiments of the inventions has been presented for the purposes of illustration and description. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the inventions not be limited solely to the description above. 

1. An integrated circuit device comprising: a memory cell including a transistor, the transistor comprising a gate, a body region configured to be electrically floating, and a source region and a drain region adjacent the body region; and refresh circuitry coupled to the memory cell, the refresh circuitry configured to refresh data of the transistor by sequentially applying to the transistor, during a single clock cycle, read control signals and one of first write control signals and second write control signals.
 2. The integrated circuit device of claim 1, wherein the refresh circuitry is configured to refresh data of the transistor by applying to the transistor voltage levels substantially the same as read control signals.
 3. The integrated circuit device of claim 1, wherein the read control signals include a first gate signal applied to a gate of the transistor and a first potential difference applied between a source and a drain of the transistor.
 4. The integrated circuit device of claim 3, wherein the first gate signal includes a voltage approximately in a range of −1.2 volts to zero (0) volts.
 5. The integrated circuit device of claim 1, wherein the refresh circuitry is configured to apply the first write control signals to the transistor when detecting a logic high data state in the transistor in response to the applying of the read control signals.
 6. The integrated circuit device of claim 1, wherein the refresh circuitry is configured to apply the second write control signals to the transistor when detecting a logic low data state in the transistor in response to the applying of the read control signals.
 7. The integrated circuit device of claim 1, wherein the first write control signals and second write control signals include a second gate signal applied to the gate.
 8. The integrated circuit device of claim 7, wherein the second gate signal includes a voltage approximately in a range of zero (0) volts to one (1) volt.
 9. The integrated circuit device of claim 7, wherein the first write control signals include signals having a second potential difference applied between a source and a drain of the transistor.
 10. The integrated circuit device of claim 9, wherein the second potential difference is configured to refresh a logic high data state in the transistor.
 11. The integrated circuit device of claim 10, wherein the second potential difference is greater than a threshold at which current flows in the body region of the transistor.
 12. The integrated circuit device of claim 7, wherein the second write control signals include signals having a third potential difference applied between a source and a drain of the transistor.
 13. The integrated circuit device of claim 12, wherein the third potential difference is configured to refresh a logic low data state in the transistor.
 14. The integrated circuit device of claim 13, wherein the third potential difference is less than a threshold at which current flows in the body region of the transistor.
 15. The integrated circuit device of claim 7, wherein the first write control signals include signals having a second potential difference applied between a source and a drain of the transistor, wherein the second write control signals include signals having a third potential difference applied between the source and the drain, wherein the second potential difference is greater than the third potential difference.
 16. The integrated circuit device of claim 1, wherein the body region functions as an inherent bipolar transistor.
 17. The integrated circuit device of claim 1, comprising data sense circuitry coupled to the memory cell, the data sense circuitry comprising a read-word line coupled to the gate and a read-bit output coupled to the source region or the drain region.
 18. The integrated circuit device of claim 17, wherein the body region stores a data bit in the form of a charge accumulated in the body region.
 19. The integrated circuit device of claim 18, wherein, in response to the read control signals, the transistor delivers the data bit onto the read-bit line by discharging the body region in response to a shifting voltage level on the read-word line.
 20. The integrated circuit device of claim 19, wherein the shifting voltage level on the read-word line provides a gate-to-source voltage sufficient to cause read-bit line charging or lack of charging depending on data state.
 21. The integrated circuit device of claim 19, wherein the discharging provides a read current at the read-bit line that is proportional to the current gain of the transistor multiplied by the charge.
 22. The integrated circuit device of claim 21, wherein the data sense circuitry determines a data state of the memory cell at least substantially based on the read current.
 23. The integrated circuit device of claim 19, wherein the transistor delivers the data bit onto the read-bit line by discharging the body region in response to a shifting voltage level on a read-source line coupled to the source region or the drain region.
 24. The integrated circuit device of claim 1, wherein the gate is disposed over a first portion of the body region.
 25. The integrated circuit device of claim 24, wherein the source region adjoins a second portion of the body region that is adjacent the first portion and separates the source region from the first portion.
 26. The integrated circuit device of claim 25, wherein the drain region adjoins a third portion of the body region that is adjacent the first portion and separates the drain region from the first portion.
 27. The integrated circuit device of claim 24, comprising a first voltage coupled to the gate, wherein the first voltage may cause minority carriers to accumulate in the first portion of the body region.
 28. The integrated circuit device of claim 27, wherein the minority carriers accumulate at a surface region of the first portion of body region that is juxtaposed or near a gate dielectric which is disposed between the gate and the first portion of the body region.
 29. The integrated circuit device of claim 27, wherein a region that includes the minority carriers is disconnected from the source region by the second portion of the body region.
 30. The integrated circuit device of claim 27, wherein a region that includes the minority carriers is disconnected from the drain region by the third portion of the body region.
 31. The integrated circuit device of claim 27, comprising a first potential difference coupled between the source and the drain, the first potential difference less than a threshold above which bipolar current is generated in the body.
 32. The integrated circuit device of claim 27, comprising a first potential difference coupled between the source and the drain, the first potential difference greater than a threshold above which bipolar current is generated in the body, wherein the first potential difference generates bipolar current in the body region as a result of impact ionization due to the presence of minority carriers in the body region.
 33. The integrated circuit device of claim 32, comprising a second voltage coupled to the gate after and instead of the first voltage, the second voltage greater than a threshold which causes an accumulation of minority carriers in the first portion of the body region, wherein the minority carriers result in the first data state which is representative of a first charge in the body region.
 34. The integrated circuit device of claim 32, comprising a second voltage coupled to the gate after and instead of the first voltage, the second voltage less than a threshold which causes an accumulation of minority carriers in the first portion of the body region.
 35. The integrated circuit device of claim 1, wherein one or more of the source region and the drain region include a doped region shaped so that a farthermost boundary of the doped region is separated from a portion of the body region underlying the gate.
 36. The integrated circuit device of claim 1, wherein the body region includes a first type of semiconductor material and the source region and drain region include a second type of semiconductor material.
 37. The integrated circuit device of claim 36, wherein the source region includes a lightly doped region.
 38. The integrated circuit device of claim 36, wherein the source region includes a highly doped region.
 39. The integrated circuit device of claim 36, wherein the source region includes a lightly doped region and a highly doped region.
 40. The integrated circuit device of claim 36, wherein the drain region includes a lightly doped region.
 41. The integrated circuit device of claim 36, wherein the drain region includes a highly doped region.
 42. The integrated circuit device of claim 36, wherein the drain region includes a lightly doped region and a highly doped region.
 43. An integrated circuit device comprising: a memory cell including a transistor, the transistor comprising a gate, a body region configured to be electrically floating, and a source region and a drain region adjacent the body region; and refresh circuitry coupled to the memory cell, the refresh circuitry configured to refresh data of the transistor by sequentially applying to the transistor, during a single clock cycle, read control signals and one of first write control signals and second write control signals, wherein voltage levels of the read control signals and the first and the second write control signals are approximately equivalent.
 44. An integrated circuit device comprising: a memory cell consisting essentially of one transistor, the transistor comprising, a gate; an electrically floating body region; and a source region and a drain region adjacent the body region; and refresh circuitry coupled to the memory cell, the refresh circuitry configured to refresh data of the transistor by applying to the transistor, during a single clock cycle, read control signals followed by write control signals.
 45. The integrated circuit device of claim 44, wherein the read control signals include a first gate signal applied to a gate of the transistor and a first potential difference applied between a source and a drain of the transistor.
 46. The integrated circuit device of claim 45, wherein the first gate signal includes a voltage approximately in a range of −1.2 volts to zero (0) volts.
 47. The integrated circuit device of claim 44, wherein the write control signals comprise one of first write control signals and second write control signals.
 48. The integrated circuit device of claim 47, wherein the refresh circuitry is configured to apply the first write control signals to the transistor when detecting a logic high data state in the transistor in response to the applying of the read control signals.
 49. The integrated circuit device of claim 47, wherein the refresh circuitry is configured to apply the second write control signals to the transistor when detecting a logic low data state in the transistor in response to the applying of the read control signals.
 50. The integrated circuit device of claim 47, wherein the first write control signals and second write control signals include a second gate signal applied to the gate.
 51. The integrated circuit device of claim 50, wherein the second gate signal includes a voltage approximately in a range of zero (0) volts to one (1) volt.
 52. The integrated circuit device of claim 50, wherein the first write control signals include signals having a second potential difference applied between a source and a drain of the transistor.
 53. The integrated circuit device of claim 52, wherein the second potential difference is configured to refresh a logic high data state in the transistor.
 54. The integrated circuit device of claim 53, wherein the second potential difference is greater than a threshold at which current flows in the body region of the transistor.
 55. The integrated circuit device of claim 50, wherein the second write control signals include signals having a third potential difference applied between a source and a drain of the transistor.
 56. The integrated circuit device of claim 55, wherein the third potential difference is configured to refresh a logic low data state in the transistor.
 57. The integrated circuit device of claim 56, wherein the third potential difference is less than a threshold at which current flows in the body region of the transistor.
 58. The integrated circuit device of claim 50, wherein the first write control signals include signals having a second potential difference applied between a source and a drain of the transistor, wherein the second write control signals include signals having a third potential difference applied between the source and the drain, wherein the second potential difference is greater than the third potential difference.
 59. A method for refreshing a memory cell comprising a transistor configured to include a floating body, the method comprising sequentially applying read control signals and refresh control signals to the transistor during a single clock cycle, the refresh control signals comprising one of first write control signals to refresh a first data state and second write control signals to refresh a second data state.
 60. The method of claim 59, comprising selecting one of the first and the second write control signals in response to a data state detected in the transistor during the applying of the read control signals.
 61. The method of claim 59, wherein the applying of the read control signals comprises applying a first gate signal to a gate of the transistor, wherein the applying of the read control signals comprises applying a source signal to a source of the transistor and a drain signal to a drain of the transistor, wherein a first potential difference is applied between the source and the drain.
 62. The method of claim 59, wherein the applying of the refresh control signals comprises applying a second gate signal to a gate of the transistor.
 63. The method of claim 59, comprising detecting a logic high data state in the floating body in response to the applying of the read control signals.
 64. The method of claim 63, wherein the first write control signals are configured to refresh a logic high data state in the transistor.
 65. The method of claim 63, wherein the applying of the first write control signals comprises generating a second potential difference between a source and a drain of the transistor, the second potential difference being greater than a threshold at which current flows in the transistor.
 66. The method of claim 59, comprising detecting a logic low data state in the transistor.
 67. The method of claim 66, wherein the second write control signals are configured to refresh a logic low data state in the transistor.
 68. The method of claim 66, wherein the applying of the second write control signals comprises generating a third potential difference between a source and a drain of the transistor, the third potential difference being less than a threshold at which current flows in the transistor.
 69. A method for refreshing a memory cell, comprising: applying read control signals to a transistor during a clock cycle, the read control signals including a first gate signal applied to a gate of the transistor and a first potential difference applied between a source and a drain of the transistor, wherein a body region of the transistor is configured to be electrically floating; and applying write control signals to the transistor during the clock cycle and following the read control signals, the write control signals including a second gate signal applied to the gate and a second or third potential difference applied between a source and a drain of the transistor depending on data state detected in the transistor during the applying of the read control signals.
 70. The method of claim 69, comprising detecting a logic high data state in the body region in response to the read control signals.
 71. The method of claim 70, wherein the second potential difference is configured to refresh the logic high data state.
 72. The method of claim 71, wherein the second potential difference is greater than a threshold at which current flows in the body region.
 73. The method of claim 69, comprising detecting a logic low data state in the body region.
 74. The method of claim 73, wherein the third potential difference is configured to refresh the logic low data state.
 75. The method of claim 74, wherein the third potential difference is less than a threshold at which current flows in the body region. 